1. Field of the Invention
The present invention relates to a semiconductor output circuit serving as an interface circuit between LSIs operating with different supply voltages and to a computer system employing the semiconductor output circuit.
2. Description of the Prior Art
Given the increasing demands of portable applications and the increased complexity and density associated with scaled LSIs, the need to control power dissipation and power consumption has become essential. This requires the LSI to operate with lower supply voltages. The tendency of the reduction of operation voltages of LSIs will rise further from 3, 2 to 1 Volt or sub 1 Volt in the future. During a migration period of the operating voltages of LSIs, such as going from 5 Volts to 3 Volts, or from 3 Volts to 2 Volts, a mixture of LSIs operating with different supply voltages will be used, and there is a need of an interface circuit mediating between the different operation voltages. For example, there is a need of an interface circuit for bridging a 5-V circuit and a 3-V circuit.
FIG. 1 shows a semiconductor output circuit serving as an interface circuit according to a first prior art. The circuit has a pre-buffer 201 for driving and inverting an input signal IN. The output of the pre-buffer 201 is connected to a node N201, which is connected to the gate of an enhancement-type (E-type) p-channel MOS transistor 202. Any p-channel MOS transistor is referred to as "pMOS" in this specification. The source and substrate of the pMOS 202 are connected to a low-voltage power source VCC for providing 3 V, and the drain thereof is connected to a node N202. The pMOS 202 serves as a pull-up circuit for providing the node N202 with 3 V. The term "substrate" in this specification is used to explain an equivalent circuit of a semiconductor circuit and is not always equal to the substrate of an actual semiconductor chip. It may sometimes correspond to a well (n-well) formed in the real substrate of the semiconductor chip. A depletion-type (D-type) n-channel MOS transistor 203 is formed between the node N202 and an output pad 204. Any n-channel MOS transistor is referred to as "nMOS" in this specification. The gate of the nMOS 203 is connected to the power source VCC, the drain (or source) thereof to the node N202, the source (or drain) thereof to the output pad 204, and the substrate thereof to the ground. The output pad 204 is connected to a bus line 210, and the output pad 204 may receive a high voltage of 5 V. Therefore, the semiconductor output circuit is tolerant to 5 V. As mentioned above, the "substrate" of the nMOS 203 is not always equal to the substrate of an actual semiconductor chip. It may correspond to a p-well in the chip.
The operation of the circuit of FIG. 1 that provides a 3-V output and is tolerant to 5 V will be explained. If the output pad 204 is at the low voltage of 3 V and the input signal IN represents "1", the node N201 provides 0 V to demonstrate a pull-up state by the pMOS 202. The gate of the pMOS 202 is negatively biased with respect to the source thereof, to turn on the pMOS 202. The node N202 receives 3 V to turn on the nMOS 203 because the nMOS 203 is of D-type. The nMOS 203 transfers the voltage at the node N202 to the output pad 204.
If the nMOS 203 is of E-type, it will have a gate threshold voltage Vth to drop the voltage transferred to the output pad 204 to "3 V-Vth" (three volts minus Vth). However, the nMOS 203 of FIG. 1 is of D-type, and therefore, Vth is 0. Accordingly, there is no drop in the voltage transferred to the output pad 204.
If the output pad 204 receives the high voltage of 5 V from the bus line 210, the gate of the nMOS 203 is reversely biased, to turn off the nMOS 203. Then, the node N202 can not increase over 3 V, which is equal to the gate voltage of the nMOS 203. Accordingly, the high voltage of 5 V in the bus line 210 never causes a current to reversely flow from the output pad 204 to the low-voltage power source VCC.
The problem of the first prior art will be explained. The nMOS 203 is of D-type to fully provide the output pad 204 with the voltage of the low-voltage power source VCC (3 V). Compared with the E-type nMOS, the D-type nMOS additionally involves a channel doping ion implantation process to control the gate threshold voltage Vth. This increases the cost thereof. The output voltage of the nMOS 203 is 3 V, but this output voltage is provided by a limiting state of the nMOS 203 near the gate threshold condition thereof. Accordingly, the nMOS 203 has low driving capability when providing an output current representing "1" level.
FIG. 2A shows a semiconductor output circuit serving as an interface circuit according to a second prior art. This is disclosed in Japanese Unexamined Patent Publication No. 7-86910. An input terminal 221 receives a data signal IN, and an input terminal 222 receives an output enable signal en. The output enable signal en controls the states on the output terminal 230. An OR gate 223 provides an OR of the data signal IN and output enable signal en. An inverter 224 inverts the output enable signal en. An AND gate 225 provides an AND of the inverted enable signal and the data signal IN. An output stage circuit consists of E-type pMOSs 226 and 227 and nMOSs 228 and 229, which are connected in series between a low-voltage power source VCC for providing 3.3 V and a ground. A node between the pMOS 227 and the nMOS 228 is connected to an output terminal 230. The gate of the pull-up pMOS 226 receives the output of the OR gate 223. The gate of the pull-down nMOS 229 receives the output of the AND gate 225. The gate of the nMOS 228 is connected to the power source VCC. The gate of the pMOS 227 is connected to a node N210. E-type nMOSs 231 and 232 are connected in series between the node N210 and the ground. The nMOS 231 has a gate connected to the power source VCC. The nMOS 232 has a gate connected to the output of the inverter 224. An E-type pMOS 233 is formed between the node N210 and the output terminal 230. The pMOS 233 has a gate connected to the power source VCC. The pMOS 226 has a substrate and source both connected to the power source VCC. The nMOSs 228, 229, 231, and 232 have substrates connected to the ground. The pMOSs 227 and 233 have substrates connected to the output terminal 230. The output terminal 230 provides an output signal OUT and is connected to an external bus line 241.
If the output enable signal en represents "0" to indicate an output enabled state and if the data signal IN represents "0", the output terminal 230 provides a signal representing "1". If the data signal IN represents "1", the output terminal 230 provides a signal representing "0". Namely, this circuit carries out an inverting operation. If the output enable signal en represents "1", it is an output disabled state not to drive the bus line 241. In this case, the pMOS 226 and nMOSs 229 and 232 are all turned off, to put the output terminal 230 in a high-impedance state.
If the bus line 241 provides a high voltage of 5 V higher than 3.3 V of the power source VCC under the high-impedance state, the pMOS 233 is turned on. Then, the node N210 becomes the same voltage as the output terminal 230, to completely turn off the pMOS 227 and disconnect a current path between the output terminal 230 and the power source VCC. In this way, the second prior art blocks a reverse current flowing from the bus line 241 to the power source VCC through the output terminal 230.
FIG. 2B is a sectional view showing the reverse current preventing pMOS 227 of FIG. 2A. The substrate of the pMOS 227 is connected to the output terminal 230. As mentioned above, the "substrate" is used to explain the equivalent circuits shown in the figures, and in the actual semiconductor chip of FIG. 2B, corresponds to an n-type well region 227b. More precisely, an n.sup.+ -type contact region formed in the n-type well is connected to the output terminal 230. When the pMOSs 226 and 227 are turned on in the pull-up operation, a p-type region 227a (source) and the n-type well region 227b (substrate) form a pn diode D1 forwardly biased. As a result, the p-type region 227a, the n-type well region 227b, and a p-type region 227c cause a bipolar operation. This results in passing a large overcurrent from the power source VCC to the ground through the regions 227a, 227b, and 227c, to cause a latch-up fault to break the pMOS 227.
FIG. 3 shows a semiconductor output circuit serving as an interface circuit according to a third prior art. This circuit is disclosed in Japanese Unexamined Patent Publication No. 64-72618. A first input terminal 251 receives an input data signal IN, and a second input terminal 252 receives an output enable signal en. A NAND gate 253 provides a NAND of the data signal IN and the output enable signal en. An inverter 254 inverts the output enable signal en. A NOR gate 255 provides a NOR of the inverted output enable signal and the data signal IN. An input transistor nMOS 256 has a gate to receive the output enable signal en and is connected to an nMOS 257 in series between a node N250 and the ground. The nMOSs 256 and 257 are of E-type. NMOSs and pMOSs are of E-type in this specification unless otherwise specified. An output stage circuit includes a switching transistor pMOS 258, a pull-up transistor pMOS 259, a pass transistor nMOS 260, and a pull-down transistor nMOS 261, which are connected in series between a low-voltage power source VCC of 3.3 V and the ground. The pMOS 258 has a gate connected to the node N250. The pMOS 259 has a gate to receive the output of the NAND gate 253. The nMOS 261 has a gate to receive the output of the NOR gate 255. The nMOS 260 has a gate connected to the power source VCC.
The node N250 is connected to a node between the pMOSs 258 and 259 through a control transistor pMOS 262 having a gate connected to the second input terminal 252. A node between the pMOS 259 and the nMOS 260 is connected to an output terminal 263. An n-well bias transistor pMOS 264 has a gate connected to the output terminal 263, a source connected to the power source VCC, and a drain and substrate connected to an n-well region 270, which is connected to the substrates of the pMOSs 258, 259, and 262. The output terminal 263 is connectable to an external circuit 280.
If the output enable signal en is "1" to indicate an output enabled state and if the input data signal IN is at 3.3 V, the output terminal 263 provides a high voltage representing a first output state. If the input data signal IN is at 0 V with the output enable signal en being "1", the output terminal 263 provides a low voltage representing a second output state. If the external circuit 280 is connected to the output terminal 263, the output enable signal en is set to "0" to put the output terminal 263 in a high-impedance state.
If a high voltage of, for example, 4 V higher than 3.3 V and lower than 5.5 V is applied from the external circuit 280 to the output terminal 263 under the high-impedance state, the pMOS 259 is turned on. Then, the pMOS 262 whose gate is receiving 0 V is also turned on to supply the high voltage from the output terminal 263 to the node N250. This turns off the pMOS 258, thereby blocking a reverse current flowing from the output terminal 263 to the power source VCC.
This third prior art has a possibility of biasing the gate of the pull-up pMOS 259 connected to the output terminal 263 to 0 V even if a high voltage in the range of 3.3 V to 5.5 V is being applied to the output terminal 263. Accordingly, the pMOS 259 needs an extra process for providing a high breakdown voltage structure such as thickening a gate oxide film. This increases the number of manufacturing processes of the circuit of FIG. 3 and complicates the process designing thereof, although this circuit is basically a low-voltage circuit that requires only a low breakdown voltage process.